The invention pertains to methods of forming implant regions. In particular aspects, the invention pertains to methods of forming pocket implant regions and/or an LDD region for a bitline contact source/drain region shared between a pair of adjacent transistor gates.
Dynamic Random Access Memory (DRAM) arrays are commonly utilized semiconductor constructions. The arrays typically comprise large numbers of individual DRAM cells, with each cell typically containing a capacitor for data storage. Each capacitor is electrically connected to a source/drain region of a transistor, with the transistor gate typically being part of a wordline. A bitline is electrically connected to another source/drain region of the transistor, and the transistor gatedly connects the bitline with the capacitor.
It is common for a pair of adjacent DRAM cells to share a bitline connection. A transistor associated with one DRAM cell has a source/drain region which overlaps the source/drain region of an adjacent transistor associated with a second DRAM cell. The overlapping source/drain region is in electrical connection with a bitline contact, and accordingly the bitline contact is shared between the adjacent DRAM cells.
Exemplary processing for forming a pair of adjacent DRAM cells is described with reference to FIGS. 1-6.
Referring initially to FIG. 1, a semiconductor construction 10 is illustrated at a preliminary processing stage. Construction 10 comprises a substrate 12 having an insulative material 14 formed thereover. Substrate 12 can comprise, consist essentially of, or consist of a single crystal semiconductive material (such as, for example, monocrystalline silicon) lightly doped with an appropriate dopant (such as, for example, a p-type dopant). For instance, substrate 12 can be a monocrystalline silicon wafer background doped with p-type dopant. To aid in interpretation of the claims that follow, the terms xe2x80x9csemiconductive substratexe2x80x9d and xe2x80x9csemiconductor substratexe2x80x9d are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone, or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also to aid in interpretation of this disclosure and the claims that follow, the terms xe2x80x9cinsulativexe2x80x9d and xe2x80x9cconductivexe2x80x9d are to be understood to refer to electrically insulative and electrically conductive materials, respectively.
Insulative material 14 can comprise, for example, silicon dioxide, and can ultimately be utilized to form a so-called pad oxide layer for transistor gates.
A conductive material 16 is formed over insulative layer 14. Conductive material 16 can comprise, consist essentially of, or consist of, for example, conductively-doped silicon, such as, for example, conductively-doped polycrystalline silicon. If conductive material 16 comprises conductively-doped silicon, the dopant can be either n-type or p-type dopant, and in typical applications of forming DRAM arrays will be n-type dopant.
Conductive layers 18 and 20 are formed over conductive material 16. Conductive layers 18 and 20 can comprise, consist essentially of, or consist of metal and/or metal compounds. In an exemplary construction, layer 18 will comprise, consist essentially of, or consist of tungsten nitride; and layer 20 will comprise, consist essentially of, or consist of tungsten.
An insulative cap 22 is formed over conductive material 20. Insulative cap 22 can comprise any suitable electrically insulative material, including, for example, silicon nitride; and in particular applications will consist of silicon nitride.
Layers 14, 16, 18, 20 and 22 can collectively be referred to as a gate stack 24. It is noted that the shown gate stack is but one exemplary type of gate stack and that numerous other types of gate stacks can be utilized in forming transistor constructions. For instance, insulative material 14 can optionally not be considered part of the gate stack. Alternatively, insulative material 14 can be considered part of the gate stack and can comprise several layers of insulative materials. Also, even though three separate conductive layers are shown (16, 18 and 20) it is to be understood that more than three separate conductive layers can be utilized, or in other applications less than three separate conductive layers can be utilized. In the shown construction, typical thicknesses of layers 14, 16, 18, 20 and 22 are about 70 Angstroms, about 500 Angstroms, about 100 Angstroms, about 200 Angstroms, and about 1500 Angstroms, respectively. The drawings are utilized to illustrate respective orientations of the shown layers, and are diagrammatic illustrations only. Accordingly, respective thicknesses of the various layers are not shown to scale.
A patterned mask 26 is formed over insulative material 22. Mask 26 can comprise, for example, photoresist, and is utilized to define locations of transistor gates. If mask 26 comprises photoresist, such can be patterned utilizing photolithographic methods.
Referring to FIG. 2, a pattern is transferred from mask 26 (FIG. 1) to underlying layers 16, 18, 20 and 22 to define a pair of partially-formed transistor gates 30 and 32; and the mask is subsequently removed. The transfer of a pattern from the mask to the underlying layers can be accomplished utilizing a suitable etch. It is noted that the etch has only proceeded partially through conductive material 16, and thus leaves an unetched portion of material 16 remaining over layer 14, in addition to forming an etched portion of material 16.
The partially-formed transistor gates 30 and 32 have sidewalls 34 and 36, respectively. An opposing pair of sidewalls is associated with each transistor gate.
Referring to FIG. 3, an insulative material 40 is formed over the unetched portion of conductive material 16, as well as along the sidewalls 34 and 36 of partially-formed transistor gates 30 and 32. Additionally, insulative material 40 extends over tops of the partially-formed transistor gates 30 and 32. Insulative material 40 can comprise any suitable material, and, in exemplary applications, comprises, consists essentially of, or consists of silicon nitride.
Referring to FIG. 4, layer 40 is anisotropically etched to form sidewall spacers 42 and 44 along the sidewalls 34 and 36, respectively. After formation of spacers 42 and 44, an etch is utilized to extend the opening through the remaining portion of conductive material 16, as well as through insulative material 14. The etch completes formation of transistor gates 30 and 32, and exposes a surface of substrate 12 between the transistor gates. It is to be understood, however, that in other processing (not shown) the opening can be extended through the remaining portion of conductive material 16, but not through insulative material 14; and accordingly material 14 can be left over an upper surface of substrate 12 after the etch.
In applications in which insulative cap 22 consists of silicon nitride, sidewall spacers 42 and 44 consist of silicon nitride, and in which conductive material 16 consists of conductively-doped silicon, a suitable etch for conductive material 16 is an etch selective for conductively-doped silicon relative to silicon nitride.
After etching through the remaining portion of conductive material 16, source/drain regions 46, 48 and 50 can be formed proximate the transistor gates utilizing an appropriate implant. For instance, the source/drain regions can be heavily-doped n-type regions, and accordingly can be formed utilizing a suitable implant of n-type dopant. As shown, the regions are self-aligned relative to transistor gates 30 and 32 since the transistor gates 30 and 32 are effectively utilized as a mask during the formation of the source/drain regions.
A first transistor device 52 can be considered to comprise transistor gate 30 in combination with source/drain regions 46 and 48; and a second transistor device 54 can be considered to comprise transistor gate 32 together with source/drain regions 48 and 50. Accordingly, source/drain region 48 is shared by the first and second transistor devices 52 and 54.
A masking material 60 is formed over transistor devices 52 and 54. Masking material 60 can comprise, for example, photoresist.
Referring to FIG. 5, masking material 60 is patterned to form an opening 62 extending to shared source/drain region 48. If masking material 60 comprises photoresist, opening 62 can be formed utilizing photolithographic processing methods.
A problem which can occur during formation of opening 62 through the large amount of photoresist material 60 is that a small amount of photoresist material can remain at the bottom of the opening as a so-called scum 64. The amount of photoresist material remaining at the bottom of the opening is variable. In typical processing, an array of devices will be formed. Accordingly, the two devices shown being patterned would correspond to a small portion of a large array of devices, with such array typically comprising thousands of devices, and accordingly thousands of openings would be formed between the devices. The variable amount of scum 64 within the various openings can complicate subsequent procedures, in that it can lead to non-uniformity of the procedures across the various openings.
A dopant 66 is implanted at an angle into substrate 12 to form pocket implant regions 68 and 70 relative to the transistor devices 52 and 54, respectively. Implant 66 is referred to as an xe2x80x9cangledxe2x80x9d implant, to emphasize that the implant is at an angle other than 0xc2x0 relative to a vertical direction. In the diagram of FIG. 5, an axis 68 is provided to illustrate a vertical direction (such direction is substantially orthogonal to a substantially planar upper surface of substrate 12), and an angle xcex8 is provided to shown the relative angle of implant 66 to the vertical direction. Angle xcex8 has an absolute magnitude greater than 0xc2x0.
Dopant 66 can be either a p-type dopant or an n-type dopant, and can be of the same conductivity type as the dopant utilized for forming heavily-doped source/drain region 48 or of an opposite dopant type. In exemplary processing, dopant 66 will be of an opposite dopant type to the dopant utilized for forming source/drain region 48, and accordingly pocket implant region 68 and 70 can be halo regions relative to heavily-doped source/drain region 48. The pocket implant regions can comprise a lower concentration of dopant than the heavily-doped regions. For instance, the heavily-doped regions can comprise at least about 1021 atoms/cm3 of dopant and the pocket implant regions can comprise from about 1019 atoms/cm3 to about 5xc3x971020 atoms/cm3.
An additional implant which can be performed at the processing stage of FIG. 5 is a lightly doped diffusion (LDD) implant. The LDD implant is typically straight into substrate 12 (i.e., implanted with angle xcex8 of 0 degrees), and forms a region overlapping region 48. The dopant of the LDD implant can subsequently be diffused to extend outwardly beyond region 48. The LDD implant is not shown in FIG. 5. The LDD region would typically formed to have a dopant concentration of from about 1019 atoms/cm3 to about 5xc3x971020 atoms/cm3.
Problems which can occur during the processing of FIG. 5 are that the variable thickness of scum 64 amongst various openings of an array can cause implant regions 68 and 70 to have different depths across the array, and can also cause LDD implant regions to have different depths across the array. The differing depths of the LDD implant region and of regions 68 and 70 can undesirably create variances in device performance across the array.
Referring to FIG. 6, mask 60 and scum 64 (FIG. 5) are stripped from construction 10 and ultimately transistor devices 52 and 54 are incorporated into a pair of DRAM cells. Specifically, source/drain regions 46 and 50 are electrically connected to storage nodes of capacitor constructions 72 and 74, respectively, and source/drain region 48 is electrically connected to a bitline 76. In the shown exemplary construction, spacers 80 and 82 have been formed outwardly of spacers 42 and 44 to cover exposed conductive surfaces 84 of conductive material 16. Spacers 80 and 82 can comprise any suitable insulative material, and can, in particular aspects, consist of one or both of silicon dioxide and silicon nitride. Spacers 80 can be formed by providing one or more layers of insulative material over substrate 12 and transistor gates 30 and 32, and subsequently anisotropically etching the insulative material. It is noted that although heavily doped source/drain regions 46, 48 and 50 are shown formed before spacers 80 and 82, the heavily doped source/drain regions can alternatively be implanted after the formation of spacers 80 and 82.
The construction of FIG. 6 can be considered to comprise a pair of DRAM cells. Specifically, a first DRAM cell can be considered to include first transistor device 52 together with capacitor 72, and a second DRAM cell can be considered to comprise second transistor 54 in combination with capacitor 74.
The invention includes methods of forming implant regions relative to transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form one or more implant regions beneath and/or between the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The one or more implant regions can correspond to pocket implant regions and/or to an LDD region. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies. In a particular application, the gates are incorporated into a pair of adjacent DRAM cells, with the adjacent DRAM cells sharing a bitline contact.